Frame-Transfer charged coupled image sensors have an architecture similar to that of full-frame CCDs. These devices have a parallel register that is divided into two separate and identical areas, termed the Image and Storage arrays. Instructions for operation of the tutorial appear below the applet window.

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The image array consists of a light-sensitive photodiode register, which acts as the image plane and collects incoming photons projected onto the CCD surface by the camera or microscope lenses. After image data has been collected and converted into electrical potential by the image array, the data is then quickly shifted in a parallel transfer to the storage array for readout by the serial shift register.

The storage array is illustrated as a large area of gray-scale "pixels" covered with an opaque mask in this interactive Java tutorial. Like the full-frame architecture, the frame-transfer CCD undergoes readout by shifting rows of image information in a parallel fashion, one row at a time, to the serial shift register. The serial register then sequentially shifts each row of image information to an output amplifier as a serial data stream. This action is controlled by the CCD Speed slider in the tutorial. Use the mouse cursor to shift the slider to the left to observe the CCD at slower shift speeds, or to the right for faster speeds. The entire process is repeated until all rows of image data are transferred to the output amplifier and off the chip to a analog-to-digital signal converter integrated circuit. Reconstruction of the image in a digital format yields the final photograph or photomicrograph.

During the period in which the parallel storage array is being read, the image array is busy integrating charge for the next image frame. A major advantage of this architecture is the ability of this device to operate without a shutter or synchronized strobe, allowing for an increase in device speed and faster frame rates. Frame-transfer CCDs suffer from several drawbacks including image "smear", which occurs because integration and dump to the storage array occur simultaneously. These devices are also more costly to produce because twice the silicon area is required to implement the architecture, resulting in lower image resolution and higher cost.